1. Field of the Invention
The present disclosure relates to an apparatus and a method for controlling data interface.
2. Discussion of the Related Art
A low-voltage differential signaling (LVDS) interface has been used as an interface for data transmission in most liquid crystal displays. However, the LVDS interface cannot properly cope with an increase in the amount of data resulting from a double speed drive or a quad-speed drive for a high resolution, color depth extension, response time improvement of the liquid crystal displays. When the LVDS interface is adapted to a 120 Hz Full HD (1920×1080) panel of 10-bit color depth, 24 pairs of lines, i.e., 48 lines total, are required. The LVDS interface is used to transmit clock signals as well as the data. Thus, as the amount of data to be transmitted increases, a frequency of the clock signal of the LVDS interface also increases. Hence, electromagnetic interference (EMI) has to be controlled.
According to a standard of the LVDS interface, the LVDS interface transmits signals changing around a voltage of 1.2V to ground. A standard of a signal voltage required in the LVDS interface took a large limit to a design of large scale integration (LSI) because of the achievement of a fine process of the LSI. In this situation, an interface such as a digital video interface (DVI), a high definition multimedia interface (HDMI), DisplayPort was proposed and was put to practical use.
The DVI and the HDMI each have a skew adjustment function, and high-bandwidth digital content protection (HDCP) may be embedded in HDMI as a content protection function. Therefore, the DVI and the HDMI have a great advantage in the transmission of an image signal between devices. However, in addition to licensing cost, DVI and HDMI require substantial power consumption and have excessive functions for the transmission of the image signal between the devices.
DisplayPort interface was standardized as a specification capable of replacing the LVDS interface in video electronics standards association (VESA). The DisplayPort (DP) interface can monitor the operating condition of the receiving terminal (Rx) at the transmitting terminal (Tx) via the auxiliary (AUX) channel. Because the HDCP is embedded in DisplayPort (DP) interface in consideration of transmission of protected content between the devices in the same manner as the HDMI, DisplayPort (DP) interface also has excessive functions and requires substantial power consumption. Further, when DisplayPort performs the signal transmission at a low frequency, a loss is generated in DisplayPort because a transmission speed of the DisplayPort is fixed. Thus, a receiving terminal of the DisplayPort has to reproduce clock signals.
V-by-One interface was developed by THine Electronics, Inc. The V-by-One interface has better signal transmission quality than the existing LVDS interface due to the introduction of an equalizer function and has also realized 3.75 Gbps per 1 Pair. Further, the V-by-One interface solved the problem of the skew adjustment generated in the clock transmission of the LVDS interface because the transmitting terminal (Vx1 Tx) does not send clocks due to the adoption of clock data recovery (CDR). Because the V-by-One interface does not have the clock transmission function required in the existing LVDS interface, an EMI noise resulting from the clock transmission may be reduced. Because the V-by-One interface can efficiently cope with an increase in an amount of data and the higher speed drive, the V-by-One interface is drawing attention as an alternative technology of the existing LVDS interface.
However, the V-by-one interface can not monitor the operating status/conditions of the receiving terminal (Vx1 Rx) at the transmitting terminal (Vx1 Tx). Therefore, under abnormal conditions such as the electro static discharge (ESD), the CDR lock can be occurred at the receiving terminal (Vx1 Rx) abnormally. Consequently, as this abnormal condition of the receiving terminal can not be detected at the transmitting terminal, the operating status/conditions between the transmitting terminal and the receiving terminal are not synchronized, so that it is very hard to solve the problems in which the data sent from the transmitting terminal may be missed at the receiving terminal.